VTI is redesigning the LETA chip for reasons that I won't go into here. As
a result, some specs will change:

1) The data hold time (tOH), the time that the output data are valid after
   the address has changed, is currently spec'ed at a minimum of 30 nS. The
   new parameter will probably be under 20 nS.

2) The TEST pin will become a RESET pin that will zero all the counters for
   betters testability.  The TEST pin was originally intended to feed the
   inputs to the data pins, essentially making the LETA a parallel port.
   However, this function never worked correctly so I don't think the change
   will have any effect.


If anyone knows of any problems these changes may cause, please let me know
by tomorrow, Sep. 5.

Thanks,
  -- Don